The present invention relates generally to microclectromechanical systems (MEMS), and more particularly to the design and fabrication of interconnect architectures for MEMS.
MEMS can include numerous electromechanical devices fabricated on a single substrate, many of which are to be separately actuated in order to achieve a desired operation. For example, a MEMS optical switch may include numerous mirrors that are each positionable in a desired orientation for reflecting optical signals between originating and target locations upon actuation of one or more microactuators associated with each mirror. In order for each mirror to be separately positioned, separate control signals need to be supplied to the microactuators associated with each mirror. One manner of accomplishing this is to connect each microactuator to a control signal source with a separate electrical conductor (i.e., an interconnect line) fabricated on the surface of the substrate that extends between its associated microactuator and a bond pad at the periphery of the substrate where it can be easily connected to an off-chip control signal source. In this regard, the separate interconnect lines together comprise an interconnect bus and are typically arranged to run parallel with each other for substantial portions of their length.
As may be appreciated, the amount of footprint required on the surface of the substrate for an interconnect bus is an important factor in designing MEMS since increasing the footprint of the interconnect bus decreases the amount of footprint available for desired devices (e.g., mirrors and actuators). Another consideration is possible cross-talk between the separate interconnect lines. Cross-talk is a problem because a control signal intended for one actuator can be coupled from its interconnect line into adjacent interconnect lines causing undesired actuation of other actuators. A further consideration is the possibility of shorting between adjacent interconnect lines. Where the interconnect bus lines are exposed on the surface of the substrate, particles and the like can settle across adjacent interconnect lines thereby causing short circuits effecting operation of the MEMS.
Accordingly, the present invention provides a shielded multi-conductor interconnect bus for MEMS and a method for fabricating such an interconnect bus. The shielded multi-conductor interconnect bus of the present invention substantially reduces the possibility of cross-talk between adjacent interconnect lines, alleviates the possibility of short circuits due to particles and the like settling across adjacent interconnect lines, and optimizes the amount of footprint required for such an interconnect bus.
According to a first aspect of the present invention, a multi-level shielded multi-conductor interconnect bus is provided having first and second levels of shielded electrically conductive lines. The second level electrically conductive lines may be oriented parallel with the first level electrically conductive lines or they may be oriented transverse to the first level electrically conductive lines. The multi-level shielded multi-conductor interconnect bus includes a substrate. The substrate may, for example, be comprised of silicon. A first dielectric layer overlies and is supported by at least a portion of the substrate. In this regard, the first dielectric layer may, for example, be the lowest layer of material on the substrate (i.e., it may be formed directly on the upper surface of the substrate without any intervening layers). In one embodiment, the substrate is comprised of silicon and the first dielectric layer comprises a dielectric stack deposited directly on the upper surface of the substrate that includes a lower layer of thermal oxide and an upper layer of silicon nitride. A plurality of substantially parallel first level electrically conductive lines are formed on the first dielectric layer. A first level electrically conductive shield is formed in a spaced relation above the first level electrically conductive lines. A plurality of first level electrically conductive walls are formed on the first dielectric layer. Although desirable, it should be understood that electrically conductive walls described herein do not have to be continuous along their lengthwise extent and may, in fact, have one or more breaks formed therein as desired. The first level electrically conductive walls typically extend parallel with the first level electrically conductive lines and include upper sections in contact along at least a portion thereof with a lower side of the first level electrically conductive shield. The first level electrically conductive lines and the first level electrically conductive walls are arranged in pattern such that at least one first level electrically conductive wall is located between sets of the first level electrically conductive lines, with each set of first level electrically conductive lines including at least one first level electrically conductive line.
The first dielectric layer may also include a plurality of first channels formed therein with lower sections of the first level electrically conductive walls being formed in the first channels. Where the first dielectric layer is the lowest layer of material on the substrate, each first channel preferably extends vertically downward through the entire thickness of the first dielectric layer along at least a portion of each first channel, and, more preferably along the entire length of each first channel to permit the lower sections of the first level electrically conductive walls to contact the upper surface of the substrate.
The multi-level shielded multi-conductor interconnect bus also includes a plurality of substantially parallel second level electrically conductive lines formed in a spaced relation above the first level electrically conductive shield. A second level electrically conductive shield is formed in a spaced relation above the second level electrically conductive lines. A plurality of second level electrically conductive walls are formed above the first level electrically conductive shield. The second level electrically conductive walls typically extend parallel with the second level electrically conductive lines and include lower sections in contact along at least a portion thereof with an upper side of the first level electrically conductive shield and upper sections in contact along at least a portion thereof with a lower side of the second level electrically conductive shield. The second level electrically conductive lines and second level electrically conductive walls are arranged in pattern such that at least one of the second level electrically conductive walls is located between sets of second level electrically conductive lines, with each set of second level electrically conductive lines including at least one second level electrically conductive line.
In one embodiment, the first level electrically conductive lines and the lower sections of the first level electrically conductive walls are formed from a first layer of doped polysilicon, the upper sections of the first level electrically conductive walls and the first level electrically conductive shield are formed from a second layer of doped polysilicon (which may be comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon), the second level electrically conductive lines and the lower sections of the second level electrically conductive walls are formed from a third layer of doped polysilicon, and the second level electrically shield and the upper sections of the second level electrically conductive walls are formed from a fourth layer of doped polysilicon.
The first and second level electrically conductive lines may be surrounded by dielectric material. In this regard, the multi-level shielded multi-conductor interconnect bus may also include second, third and fourth layers of dielectric material (e.g., silicon dioxide or silicate glass). The second dielectric layer overlies the first level electrically conductive lines and first dielectric layer and includes a plurality of channels formed therein permitting the upper sections of the first level electrically conductive walls to extend vertically upward therethrough to contact the first level electrically conductive shield. The third dielectric layer overlies the first level electrically conductive shield and includes a plurality of channels formed therein permitting the lower sections of the second level electrically conductive walls to extend vertically downward therethrough to contact the first level electrically conductive shield. The fourth dielectric layer overlies the second level electrically conductive lines and third dielectric layer and includes a plurality of channels formed therein permitting the upper sections of the second level electrically conductive walls to extend vertically upward therethrough to contact the second level electrically conductive shield. Where there is no dielectric material around the second level electrically conductive lines, there may be a plurality of anchor posts supporting the second level electrically conductive lines in the spaced relation above the first level electrically conductive shield.
It should be noted that a multi-level shielded multi-conductor interconnect bus in accordance with the present invention may be fabricated on a substrate that has one or more intervening layers of electrically conductive material and/or dielectric material between the upper surface of the substrate and the first layer of dielectric material. In this regard, the channels in the first dielectric layer extend vertically down into the first dielectric layer to expose the upper surface of an intervening layer of electrically conductive material, and the lower sections of the first level electrically conductive walls contact the intervening layer of electrically conductive material, rather than the substrate.
According to another aspect of the present invention, a three-level shielded multi-conductor interconnect bus includes a substrate and first, second, third, and fourth layers of electrically conductive material deposited over and supported by at least a portion of the substrate. A plurality of first level electrically conductive lines are formed in the first layer of electrically conductive material, a plurality of first level electrically conductive walls are formed in the first layer of electrically conductive material, a plurality of second level electrically conductive lines are formed in the second layer of electrically conductive material, a plurality of second level electrically conductive walls are formed in the second layer of electrically conductive material, a plurality of third level electrically conductive lines are formed in the third layer of electrically conductive material, a plurality of third level electrically conductive walls are formed in the third layer of electrically conductive material, and an electrically conductive shield is formed in the fourth layer of electrically conductive material. In this regard, the first, second and third level electrically conductive lines and the first, second and third level electrically conductive walls may be substantially parallel with one another. The layers of electrically conductive material may, for example, be comprised of doped polysilicon. In one embodiment, the second layer of electrically conductive material is comprised of two separately deposited layers of doped polysilicon.
The three-level shielded multi-conductor interconnect bus may also include a first layer of dielectric material (e.g. thermal oxide and silicon nitride) and second, third and fourth layers of dielectric material (e.g., silicon dioxide or silicate glass) deposited over and supported by at least a portion of the substrate. The first layer of dielectric material is disposed between the first level electrically conductive lines and the substrate, the second layer of dielectric material is disposed between the second level electrically conductive lines and the first level electrically conductive lines, the third layer of dielectric material is disposed between the third level electrically conductive lines and the second level electrically conductive lines, and the fourth layer of dielectric material is disposed between the electrically conductive shield and the third level electrically conductive lines.
According to a further aspect of the present invention, a method for making a multi-level shielded multi-conductor interconnect bus begins with removing portions of a first layer of dielectric material overlying and supported by at least a portion of a substrate to provide a plurality of substantially parallel first channels in the first layer of dielectric material. In this regard, where the first layer of dielectric material comprises a dielectric stack on an upper surface of the substrate, sufficient material may be removed so that the first channels extend vertically downward through the entirety of the dielectric stack to expose the upper surface of the substrate preferably along at least a portion of each first channel, and, more preferably, along the entire length of each first channel. A first layer of electrically conductive material is then deposited over the first layer of dielectric material, with the first layer of electrically conductive material also filling the first channels. Strips of the first layer of electrically conductive material are then removed to provide a plurality of first level electrically conductive lines typically extending parallel with the first channels. In this regard, an upper surface of the first layer of dielectric material is exposed at the bottom of each strip removed from the first layer of electrically conductive material. A second layer of dielectric material is then deposited over the first layer of electrically conductive material, with the second layer of dielectric material also filling the strips removed from the first layer of electrically conductive material. Portions of the second layer of dielectric material are removed to provide a plurality of substantially parallel second channels in the second layer of dielectric material. The second channels are located to overlie and are oriented in the same direction as the first channels and extend downward through the second layer of dielectric material to expose the first layer of electrically conductive material filling the first channels. A second layer of electrically conductive material is deposited over the second layer of dielectric material, with the second layer of electrically conductive material filling in the second channels. In one embodiment, the step of depositing a second layer of electrically conductive material may comprise the steps of depositing a lower layer of doped polysilicon, depositing an intervening layer of sacrificial material, removing the intervening layer of sacrificial material, and depositing an upper layer of doped polysilicon.
After the second layer of electrically conductive material is deposited, a third layer of dielectric material is deposited over the second layer of electrically conductive material. Portions of the third layer of dielectric material are removed to provide a plurality of substantially parallel third channels in the third layer of dielectric material. In this regard, the third channels extend downward through the third layer of dielectric material to expose the second layer of electrically conductive material at the bottom of each third channel. A third layer of electrically conductive material is deposited over the third layer of dielectric material, with the third layer of electrically conductive material also filling the third channels. Strips of the third layer of electrically conductive material are removed to provide a plurality of second level electrically conductive lines typically extending parallel with the third channels. In this regard, an upper surface of the third layer of dielectric material is exposed at the bottom of each strip removed from the third layer of electrically conductive material. A fourth layer of dielectric material is deposited over the third layer of electrically conductive material, with the fourth layer of dielectric material also filling the strips removed from the third layer of electrically conductive material. Portions of the fourth layer of dielectric material are removed to provide a plurality of substantially parallel fourth channels in the fourth layer of dielectric material. The fourth channels are located to overlie and are oriented in the same direction as the third channels and extend downward through the fourth layer of dielectric material to expose the third layer of electrically conductive material filling the third channels. The multi-level multi-conductor interconnect bus is completed by depositing a fourth layer of electrically conductive material over the fourth layer of dielectric material, with the fourth layer of electrically conductive material also filling the fourth channels.